1. Technical Field
The present invention relates generally to pulse-width modulated controls, and more particularly to controlling current to a linear solenoid in an electromagnetic-type solenoid or actuator to regulate the degree of opening of the solenoid or the amount of actuator displacement of a driven target.
2. Related Art
Linear solenoids are provided in conventional solenoids or actuators to regulate actuation of the solenoid/actuator by regulating the amount of current flow to the solenoid/actuator. In turn, current flow to the linear solenoid is typically controlled by connecting the inductive load of the linear solenoid to a direct-current power source across a switching element, such as a conducting unit including a transistor, and then switching the element on and off via controlled duty pulse-width-modulated signals.
When it is necessary to accurately control the opening degree of the solenoid or the amount of displacement of the driven target, current flowing to the linear solenoid inductive load is detected, and current feedback is performed to increase or reduce the duty of the pulse-width-modulated signals to the switching element so that the detected current value converges to a calculated target current.
Herein, in an inductive load conductivity controller that performs the above-described current control according to the prior art, a processing portion including a central processing unit (CPU) calculates the duty of the pulse-width-modulated signals at each iteration of a predetermined processing cycle. A pulse-width-modulated signal-output portion including a logic circuit and provided separately from the processing portion outputs signals to the switching element at a duty calculated by the processing portion.
More particularly, the processing portion determines the time per pulse-width-modulated signal cycle to switch the switching element on or off based on the calculated duty, and stores data representing the time in a RAM. Meanwhile, the signal-output portion includes a counter to repeatedly clock one cycle of pulse-width-modulated signals, and a register to which data stored in the specific address in the RAM is sent. The signal-output portion generates and outputs the pulse-width-modulated signal of the duty calculated by the CPU by repeating operation wherein a pulse-width-modulated signal goes to a high level (or to a low level) at the start of one cycle of a pulse-width-modulated signal detected based on the value of a counter. Correspondingly, the output portion sends the data stored in the specific address in the RAM by the processing unit to the register, and inverts the output level of the pulse-width-modulated signal when the value of a counter reaches the data value in the register.
Accordingly, pulse-width-modulated signals having a desired duty can be output to the switching element as drive signals, with no need for the processing portion to execute complex output signal processing.
However, in the above-described conventional pulse-width-modulated signal-output portion, a maximum time of one pulse-width-modulated signal cycle is required until the duty calculated by the processing portion is actually reflected in the drive for the switching element. Therefore, the actual responsiveness that can be effected when controlling the current to the inductive load is limited. That is to say, the pulse-width-modulated signal-output portion is structured so that, at the start point of one pulse-width-modulated signal cycle, the pulse-width-modulated signal-output portion transfers the data stored in the specific address of the RAM at that time to its own register. Because of this, even when the processing portion calculates the newest duty and stores the data corresponding thereto in the specified address in the RAM during one pulse-width-modulated signal cycle, the newest data is reflected only in the next pulse-width-modulated signal cycle.
To overcome the above limitation, Japanese Patent Application Laid-open No. Hei 10-2248 proposes an apparatus to monitor whether data in the foregoing specific address in the RAM has been updated by the processing portion during the interval from initiation of clocking of one pulse-width-modulated signal cycle by the counter until initiation of clocking of the next cycle. Accordingly, when a data update is detected, the apparatus transfers the updated data from the RAM to its own register, while continuously comparing the value of the counter with the data value within the above-mentioned register. When the counter value has not reached the value of the data in the register, the apparatus causes the pulse-width-modulated signals to go to one level. When the value has reached the value of the data in the register, the apparatus causes the signals to go to the other level.
Although the newest data stored at a specific address in the RAM can immediately be reflected in the duty of the pulse-width-modulated signals, the signal level may change three or more times during a single pulse-width-modulated signal cycle. As such, during one pulse-width-modulated signal cycle, after the signal level has already been reflected, the signal level is returned to its original level, and thereafter is again reflected. As a result, the pulse-width-modulated signal cycle may be disturbed.
That is to say, the signal level of the pulse-width-modulated signals ordinarily changes twice during one cycle thereof, from low to high and from high to low. However, changing of the signal level three or more times signifies a change in the pulse-width-modulated signal cycle itself. Accordingly, in a conductivity controller of the type presently discussed, the cycle of the pulse-width-modulated signals output to the switching element is established at an optimal value for adjusting the amount of displacement of the drive target, such as a solenoid or an actuator. Therefore, when division from the cycle occurs, controllability of the drive target is decreased.
Meanwhile, Japanese Patent Application Laid-open No. Hei. 6-30594, for example, describes an apparatus for generating a delta wave of the same cycle as a pulse-width-modulated signal, together with a pulse-width-modulated signal having a corresponding to a threshold value Vth. The apparatus accomplishes this by comparing the sizes of the level of the delta wave and a threshold value Vth proportional to the high-level time during one pulse-width-modulated signal cycle, and making the pulse-width-modulated go high when the level of the delta wave is the threshold value Vth or less, or otherwise making the pulse-width-modulated signal go low, as shown in FIG. 18. In the “PWM signal”. entry of FIG. 18, “ON” indicates a high level and “OFF” indicates a low level.
Accordingly, even when pulse-width-modulated signals are. generated by such a method, as shown on the right-hand half of FIG. 18, when the change timing of the threshold value Vth occurs any number of times in a single pulse-width-modulated signal cycle, disturbance occurs in the cycle of the output signals, and the controllability of the drive target decreases, as shown by the ellipse in FIG. 18.
Additionally, the above-described Japanese Patent Application Laid-open No. Hei. 6-30594 describes a structure for suppressing fluctuation of the threshold value Vth compared with the delta-wave level by a lag circuit to prevent such a problem. However, as a result of the suppression, a decline occurs even in the original reflection speed with respect to the duty of the pulse-width-modulated signals. Thus, current control responsiveness is negatively affected.
In addition, when performing the above-discussed current feedback, it is necessary to detect the load current. However, because this current flows through the switching element which is cyclically switched on and off by the pulse-width-modulated signal, the current pulses. For example, when the inductive load current is detected based on the voltage drop across a resistor provided in the conductive path of the inductive load, the detected current value fluctuates, and so stabilized control cannot be performed.
In this regard, when performing feedback control of current to an inductive load, conventionally, a current value detected using the above resistor is smoothed using a lag circuit made up of a capacitor and a resistor. The duty of the pulse-width-modulated signal is then increased or reduced in accordance with the deviation between the smoothed detected current value and the target current value, for example as shown in Japanese Patent Application Laid-open No. 60-68401.
FIG. 29 shows the general structure of a linear-solenoid controller for vehicle use. The controller controls current to a linear solenoid L incorporated within a solenoid which is a control target, to thereby control the degree of opening of various types of solenoids incorporated within a vehicle internal combustion engine, an automatic transmission or the like. As shown, in a linear-solenoid controller 1050, a host CPU 1052, which controls an internal combustion engine, an automatic transmission, or the like, issues a target current value to a linear-solenoid control IC 1054. In the linear-solenoid control IC 1054, a sub CPU 1054 receives a target current value from the host CPU 1052 and determines the duty for duty-driving the linear solenoid L based on the deviation between the target current value and the actual detected value of current flowing to the linear solenoid L. The sub CPU 1054 then outputs this duty to a pulse-width-modulated signal-output circuit 1056 as an instruction value. The circuit 1056 generates a pulse-width-modulated signal corresponding to the instruction value (duty value).
By outputting this to a switching element (in the drawing, a field-effect transistor [FET]) 1058 provided in the conduction path to the linear solenoid L from a battery which is a direct-current power source, the circuit 1056 duty-drives the switching element 58 at the duty determined by the sub CPU 1054. Additionally, a resistor R10 for current-detecting use is disposed in the conduction path of the linear solenoid L. By differentially amplifying the two end voltages of the resistor R10 with a differential amplifier 1060, the current to the linear solenoid L is converted to a voltage signal.
After the output from the differential amplifier 1060 is smoothed by a. lag circuit 1062 made up of a resistor R11 and a capacitor C11, the resulting voltage signal after being digitally converted by an analog-to-digital converter 1064 is input to the sub CPU 1054 as a detected current value indicating the current to the linear solenoid L.
However, with a current controller according to the prior art, when performing feedback control of the load current, the current detection signal is smoothed using a lag circuit or the like, the duty of the pulse-width-modulated signals is set according to this detected-current value after smoothing and a target current value, and the pulse-width-modulated signals are generated according to this duty. Because of this, considerable time is required until the current to the inductive load reaches the target current value and stabilizes, due to feedback delay, particularly delay due to the time constant of the lag circuit.
For example, when the value of the load current is controlled at the target value, as shown in FIG. 30A, when the target current value is changed (time t0), the differential between the detected current value and the target current value becomes large. Therefore, the duty of the pulse-width-modulated signals also is updated in accordance with this differential to control the detected current value at the target current value. However, when the time constant (CR time constant) of the lag circuit is large, the detected current value is such that response lag occurs with respect to change in the controlled current actually flowing to the inductive load.
Because of this, even when the controlled current reaches the target current value, the differential between the detected current value and the target current value does not reach zero, the pulse-width-modulated signals continue to be updated, the controlled current repeatedly overshoots or undershoots the target current value, and additional time is required for the controlled current to stabilize at the target current value.
For this reason, the above-described apparatus cannot be utilized where responsiveness and control precision are demanded when updating the target current value, such as in a solenoid used in changing gears in an automatic transmission.
Eliminating the lag circuit or reducing the time constant (CR time constant) thereof may increase responsiveness, but as shown in FIG. 30A, although the time until the controlled current stabilizes near the target current value is shortened, the detected current value changes in accordance with current pulsing produced duty drive of the of the switching element. Because of this, the duty of the pulse-width-modulated signals fluctuates as well. Even though the target current value is fixed, it becomes impossible to maintain the controlled current at a fixed value.
Additionally, for example in an apparatus according to the prior art shown in FIG. 29, when the cycle of pulse-width-modulated signals generated by output circuit 56 matches the processing cycle of the sub CPU 54, the sub CPU 54 must operate at high speed, and the processing load of the sub CPU 54 becomes large. Because of this, the sub CPU 54 and the output circuit 56 operate asynchronously. In such a case, it is preferable to make the processing cycle of the sub CPU 54 longer than the cycle of the output circuit 56.
However, even when the target current value is fixed and the controlled current is substantially stabilized at the target current, for example as shown in FIG. 30B, in actuality the detected current value acquired at analog-to-digital conversion timing tAD in accordance with the operation of the sub CPU 54 fluctuates due to the pulsing of the current detection signals after smoothing. Also, the duty of the pulse-width-modulated signals can be set in correspondence with the target current value.
In Japanese Patent Application Laid-open No. Hei. 5-222993, for example, an apparatus is disclosed which does not smooth current detection signals utilizing a lag circuit as in the above-described prior art. Rather, the disclosed apparatus acquires current detection signals twice, immediately after the switching element switched on and off by the pulse-width-modulated signals has been switched on, and immediately before this switching element is switched off. The apparatus determines the detected, or mean, current value from these two current values. According to this proposed apparatus, the detected current value utilized in control can be determined and can alleviate delay in the feedback system, without being affected by the time constant of a lag circuit, as in an apparatus according to the prior art which smoothes current detection signals utilizing a lag circuit.
In this proposed apparatus, the timing of the rising edge and the falling edge of the pulse-width-modulated signals changing due to control must be detected accurately, and the current detection signals must undergo analog-to-digital conversion. Consequently, a timing circuit is necessary to control the timing at which analog-to-digital conversion is performed in accordance with the rising edge and falling edge of the pulse-width-modulated signals, and the apparatus becomes complex in structure.
In the above-described current controller, the control delay for the current is produced not merely by delay in the feedback system to detect the current to the inductive load, but also by operation delay of the drive system (i.e., the pulse-width-modulated signal output circuit 56) generating the pulse-width-modulated signals in accordance with the duty calculated in accordance with the current differential.
That is to say, a pulse-width-modulated signal output circuit according to the prior art is ordinarily provided with a counter to repeatedly clock one cycle of pulse-width-modulated signals, and a register to store data expressing time for which the switching element is to be switched on or off during one pulse-width-modulated signal cycle. The apparatus generates a pulse-width-modulated signal whose signal level in inverted in correspondence with the duty by a procedure wherein at the start time of one cycle of the pulse-width-modulated signal detected based on the counter value, the pulse-width-modulated signal goes high (or low), and thereafter, the pulse-width-modulated signal is inverted when the counter value reaches the data value stored in the register.
For this reason, in a current controller according to the prior art, time equal to a maximum of one pulse-width-modulated signals cycle is required until the duty computed in correspondence with the differential between the detected current value and the target current value is reflected in the driving of the switching element, and improvement in control responsiveness is limited.